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PCDFCA May 2012 : Page 26

INTEGRATED 3D ANALYSIS 0RGHOLQJ&#03;&#16;'&#03;(IIHFWV&#03;RI&#03;&#03; 6,*1$/&#03;,17(*5,7< &#03; 3D structures on high-speed signal paths can significantly influence transmitted signals. by DR. ZHEN MU Those involved in board analysis during the past 10 years will have noticed changes in signal speed and design appli-cations. The dominant high-speed applications are high-speed memory designs and gigabit-per-second channel designs. At the end of the last century, engineers started routing differential signal nets on PCBs that could transfer data at rates exceeding 1 Gbps. The signals at such speed were initially used to build boards and backplanes in large communication systems. Demand for increasingly fast computation and information transmission continues to increase, with a substantial number of designs operating at multiple Gbps range. Advanced memory designs are moving data at 10 Gbps, and the latest SerDes communi-cation standard is reaching toward 30 Gbps. With signal speed changes come new challenges of solving design issues never seen before. The components of signal paths on boards and interconnects present problems, such as significant dielectric loss or impedance discontinuity from non-trace portion, which used to be ignored at lower signal speed. FIGURE 1A illustrates the three-dimensional cross-sec-tion of an IC with a SerDes channel, showing the die, its associated package and pins (or balls), the PCB, and the mechanical mounting of the package on the PCB; FIGURE 1B shows the electrical equivalent circuit. In this example, the impedance discontinuity contribution comes from the vias for signal switching layers, connectors enabling multi-board connections, and packages. To PCB designers, only via configurations are under their control in these discontinuity contributors. Via modeling. To understand modeling of the vias used in simulation, we’ll begin with a single via in a PCB stackup. FIGURE 2 is a schematic representation of the equivalent circuit. With slower speeds (that is, slower rise and fall times) common up to a few years ago, via effects were not significant enough to be concerned. Now, with sig-nals having rise/fall times around 100 ps, via effects are noticeable and can cause signal degradation. The typical SI effects of the impedance discontinuity caused by true 3D vias can be seen in the plots in FIGURE 3 . When simulating a complete channel, signal paths are analyzed using differential vias. Differential vias improve signal integrity, but can also cause signal degradation if the via stubs are not correctly configured. Via stubs not only cause SI issues, they can completely attenuate signals FIGURE 1. a) (top) 3D cross-section view of an IC, package, and PCB with a simplified signal critical path. b) For simula-tion purposes, this simplified electrical equivalent circuit is used to model the circuit illustrated in 1a. 26 FIGURE 2. Equivalent circuit for analyzing a single via through a PCB stackup. MAY 2012 PRINTED CIRCUIT DESIGN & FAB / CIRCUITS ASSEMBLY

INTEGRATED 3D ANALYSIS

Dr. Zhen Mu

<br /> Modeling 3D Effects of SIGNAL INTEGRITY<br /> <br /> 3D structures on high-speed signal paths can significantly influence transmitted signals.<br /> <br /> Those involved in board analysis during the past 10 years will have noticed changes in signal speed and design applications. The dominant high-speed applications are high-speed memory designs and gigabit-per-second channel designs. At the end of the last century, engineers started routing differential signal nets on PCBs that could transfer data at rates exceeding 1 Gbps. The signals at such speed were initially used to build boards and backplanes in large communication systems. Demand for increasingly fast computation and information transmission continues to increase, with a substantial number of designs operating at multiple Gbps range. Advanced memory designs are moving data at 10 Gbps, and the latest SerDes communication standard is reaching toward 30 Gbps.<br /> <br /> With signal speed changes come new challenges of solving design issues never seen before. The components of signal paths on boards and interconnects present problems, such as significant dielectric loss or impedance discontinuity from non-trace portion, which used to be ignored at lower signal speed.<br /> <br /> FIGURE 1A illustrates the three-dimensional cross-section of an IC with a SerDes channel, showing the die, its associated package and pins (or balls), the PCB, and the mechanical mounting of the package on the PCB; FIGURE 1B shows the electrical equivalent circuit. In this example, the impedance discontinuity contribution comes from the vias for signal switching layers, connectors enabling multi-board connections, and packages. To PCB designers, only via configurations are under their control in these discontinuity contributors.<br /> <br /> Via modeling. To understand modeling of the vias used in simulation, we’ll begin with a single via in a PCB stackup. FIGURE 2 is a schematic representation of the equivalent circuit. With slower speeds (that is, slower rise and fall times) common up to a few years ago, via effects were not significant enough to be concerned. Now, with signals having rise/fall times around 100 ps, via effects are noticeable and can cause signal degradation. The typical SI effects of the impedance discontinuity caused by true 3D vias can be seen in the plots in FIGURE 3.<br /> <br /> When simulating a complete channel, signal paths are analyzed using differential vias. Differential vias improve signal integrity, but can also cause signal degradation if the via stubs are not correctly configured. Via stubs not only cause SI issues, they can completely attenuate signals at certain frequencies.<br /> <br /> FIGURE 4 shows analysis on a design with a pair of differential vias on a 16-layer board. The S-parameter plot (FIGURE 4A) and the eye diagram (FIGURE 4B) illustrate how via stubs can produce unwanted resonance peaks (8 GHz in the example).<br /> <br /> The S-parameter plot shows that the via stubs (red and pink) produce several resonance points, at which point the signal component cannot be transmitted. With the stubs removed (yellow and white), there are no resonance points introduced. Similarly, the eye diagram becomes much smaller with the stubs.<br /> <br /> Effects of unused pads. The differential signal paths often enter on one layer and exit on another layer, transmitted between layers through vias. The unused via pads also can cause SI problems. FIGURE 5 shows the configuration of a pair of vias going through a board stackup of 26 layers. Leaving all these pads in place can cause a resonance peak at lower frequency. By removing the pads, the resonances are pushed upward in frequency, benefiting SI. Backdrilling is the best way to handle these problems, but removing the pads can help the problem when backdrilling is not possible.<br /> <br /> Understanding the impacts from 3D structures on signal interconnects is important for designers to ensure good design practice. However, the most common case is to know not only whether there is a design problem, but also how much the effect could be and if a design can still work without significant modification. To answer these questions, 3D modeling functions are needed to produce detailed results for studying structure behavior and making tradeoffs.<br /> <br /> Effectively using 3D modeling. When effectively putting the modeling into practice on an actual circuit, the designer has a number of questions for which he is seeking an answer. Is there an SI problem? If so, what is the magnitude and source of the problem? Can the problem be solved without significant modification, and if not, how much modification is required?<br /> <br /> Analysis tools must be capable of answering these questions quickly and accurately. Until recently, 3D analysis of a particular structure has been performed in a separate modeling environment from the general PCB (or package) layout and SI simulation tools. This is adequate for simple structures that can be manually created. But for complex or arbitrary geometries, a standalone tool requires database translation first to get structure geometries imported from layout or port-route analysis environment, which commonly is owned by third parties. In addition, the translation itself can introduce errors during conversion. Conversion can be time-consuming and risky. Also, most tools to date have required that the user have strong electromagnetic experience to use them effectively.<br /> <br /> Initial analysis should begin in the pre-layout planning stages. As you could see in the analysis of via stubs, understanding the effects of vias before actually beginning the layout can permit potential problems to be discovered and mitigated before anything has to be unraveled. For this early analysis, it is possible to use a separate 3D tool without much difficulty.<br /> <br /> Once pre-layout studies have been completed, the structure is put on board with other nets routed, components placed, and holes drilled. Even so, the resulting PCB layout can still have coupling with some components, and the previously understood behavior can be affected; there may also be new noise sources on the board after layout as well. When this happens, the discontinuity effect from the particular 3D object must be simulated again, including its immediate neighbors, such as nets, other vias, etc. At this stage of development, using a separate 3D tool to analyze the more complicated geometry is very, very tedious.<br /> <br /> Better is to have a 3D modeling engine integrated with a general layout and SI environment. The integration then permits detailed structure design/tuning in the pre-layout stage and discontinuity effect verification at port-route level. This solution is illustrated in Figure 6. In this example, Mentor Graphics’ HyperLynx was used first to specify a pair of differential vias in the pre-layout environment (FIGURE 6A) and determine if a single stitching (or ground) via is sufficient for the required switching rate.<br /> <br /> After layout, the designer can select the interested area in the routed design where other nets and structures have been placed near the vias of interest, and tell the tool to export the piece of arbitrary geometry to the 3D modeling engine for creation of proper 3D model (FIGURE 6B). The resulting model (FIGURE 6C) highlights the coupling effect to the pre-defined differential via structure. Because the position of geometry cut on the board is known, the 3D model can be connected back to the interested nets in channel simulation. Armed with these data, the designer can then decide if the channel budget can tolerate the effect, or if more design work is necessary to reduce the extra noise.

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